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CC2480
T C
I-phase
Q-phase
1
1
0
1
1
0
0
1
1
1
0
0
0
0
1
1
0
1
0
1
0
0
1
0
0
0
1
0
1
1
1
0
2T C
Figure 11: I / Q Phases when transmitting a zero-symbol chip sequence, T C = 0.5 μs
10.2 Demodulator, Symbol Synchronizer and Data Decision
The block diagram for the CC2480 demodulator
is shown in Figure 12. Channel filtering and
frequency offset compensation is performed
digitally. The signal level in the channel is
estimated to generate the RSSI level. Data
filtering is also included for enhanced
performance.
Soft decision is used at the chip level, i.e. the
demodulator does not make a decision for
each chip, only for each received symbol. De-
spreading is performed using over-sampling
symbol correlators. Symbol synchronization is
achieved by a continuous start of frame
delimiter (SFD) search.
With the ±40 ppm frequency
accuracy
The CC2480 demodulator also handles symbol
requirement from [1], a compliant receiver
must be able to compensate for up to 80 ppm
or 200 kHz. The CC2480 demodulator tolerates
up to 300 kHz offset without significant
degradation of the receiver performance.
rate errors in excess of 120 ppm without
performance degradation. Resynchronization
is performed continuously to adjust for error in
the incoming symbol rate.
I / Q Analog
IF signal
ADC
Digital
IF Channel
Filtering
Frequency
Offset
Compensation
Digital
Data
Filtering
Symbol
Correlators and
Synchronisation
Data
Symbol
Output
Average
RSSI
Generator
RSSI
Correlation
Value (may be
used for LQI)
Figure 12: Demodulator Simplified Block Diagram
10.3 Frame Format
CC2480 has hardware support for parts of the
IEEE 802.15.4 frame format. This section
gives a brief summary to the IEEE 802.15.4
frame format, and describes how CC2480 is
set up to comply with this.
Figure 13 [1] shows a schematic view of the
IEEE 802.15.4 frame format. Similar figures
describing specific frame formats (data
frames, beacon frames, acknowledgment
frames and MAC command frames) are
included in [1].
CC2480 Data Sheet SWRS074
Page 31 of 43
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